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BR34L02FV-W
● Synchronous Data Timing
Technical Note
tR
tF
tHIGH
SCL
SCL
tHD:STA
tSU:DAT tLOW
tHD:DAT
SDA
tSU:STA
tHD:STA
tSU:STO
(IN)
SDA
(OUT)
tBUF
tPD
tDH
SDA
START BIT
STOP BIT
Fig.1-(a) Synchronous Data Timing
○ SDA data is latched into the chip at the rising edge ○
of SCL clock.
○ Output data toggles at the falling edge of SCL clock.
SCL
Fig.1-(b) Start/Stop Bit Timing
SCL
DATA(1)
DATA(n)
SDA
D0
ACK
SDA
D1
D0
ACK
ACK
ｔ WR
WRITE DATA(n)
STOP CONDITION
t WR
START CONDITION
WP
tSU ： WP
Stop Condition
ｔ HD ： WP
SCL
Fig.1-(c) Write Cycle Timing
Fig.1-(d) WP Timing Of The Write Operation
DATA(1)
DATA(n)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
WP
Fig.1-(e) WP Timing Of The Write Cancel Operation
○ For WRITE operation, WP must be "Low" from the rising edge of the
clock (which takes in D0 of first byte) until the end of tWR. (See
Fig.1-(d) ) During this period, WRITE operation can be canceled by
setting WP "High". （ See Fig.1-(e) ）
○ When WP is set to "High" during tWR, WRITE operation is
immediately ceased, making the data unreliable. It must then be
re-written.
www.rohm.com
? 2009 ROHM Co., Ltd. All rights reserved.
3/17
2009.04 - Rev.A
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